[commit: stm] master: Control.Concurrent.STM.TVar: cleaning up order of exports (fc65028)

[Simon Marlow]

Repository : ssh://darcs.haskell.org//srv/darcs/packages/stm

On branch  : master

http://hackage.haskell.org/trac/ghc/changeset/fc65028d0290696eee71960c3a73b0a55a27ff86

>---------------------------------------------------------------

commit fc65028d0290696eee71960c3a73b0a55a27ff86
Author: Simon Marlow <marlowsd at gmail.com>
Date:   Mon Apr 11 11:06:14 2011 +0100

    Control.Concurrent.STM.TVar: cleaning up order of exports

>---------------------------------------------------------------

 Control/Concurrent/STM/TVar.hs |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/Control/Concurrent/STM/TVar.hs b/Control/Concurrent/STM/TVar.hs
index 8cd86a4..b3695b6 100644
--- a/Control/Concurrent/STM/TVar.hs
+++ b/Control/Concurrent/STM/TVar.hs
@@ -16,10 +16,10 @@ module Control.Concurrent.STM.TVar (
 	-- * TVars
 	TVar,
 	newTVar,
+	newTVarIO,
 	readTVar,
+	readTVarIO,
 	writeTVar,
-	newTVarIO,
-        readTVarIO,
 #ifdef __GLASGOW_HASKELL__
 	registerDelay
 #endif