[Haskell-cafe] Specialized Computer Architecture - A Question

OWP owpmailact at gmail.com
Tue Mar 19 05:16:52 CET 2013


Ironically, you made an interesting point on how Moore's Law created
the on chip "real estate" that made specialized machines possible.  As
transistor sizing shrinks and die sizes increase, more and more real
estate should now be available for usage.  Oddly, what destroyed
specialized machines in the past seemed to be the same cause in
reviving it from the dead.

The ARM Jazelle interface - I'm not familiar with it's but it's got me
curious.  Has there been any though (even in the most lighthearted
discussions) on what a physical "Haskell Machine" could look like?
Mainly, what could be left to compile to the stock architecture and
what could be sent out to more specialized areas?


On 3/18/13, Richard A. O'Keefe <ok at cs.otago.ac.nz> wrote:
>
> On 19/03/2013, at 9:31 AM, OWP wrote:
>
>> If I may ask, I'm not quite sure what O(2^n) and O(1) are?
>
> Check any data structures and algorithms textbook.
>
> Reverting to the original topic, THIS is the age of specialised
> machines.  A lot of the chips out there are not just a CPU but
> a SoC (System on a Chip).  Start with the ARM1176JZF-S chip whose
> manual I currently have open.
>  - sorta kinda RISCish ARM instruction set processor
>    + including SIMD DSP/graphics support
>  - native hardware execution of (most) Java bytecodes
>    (This is ARM's "Jazelle" extension.)
>  - vector floating point co-processor
> You can get other chips with ARM cores and a mix of
>  - analogue<->digital converters, comparators, Flash controllers,
>    Ethernet controllers, USB controllers, other interface
>    controllers, hardware encryption (especially in ARM v8),
>    more kinds of timers than you knew existed, hardware random
>    number generation,
> You can even get ARM chips with on-board FPGAs.
>
> Of course SoC systems are not limited to the ARM architecture.
> SPARC T4 chips have "Crypto Instruction Accelerators … [that] …
> enable high speed encryption for over a dozen industry standard
> ciphers" "plus random number generation" and "high speed 10 GbE
> networking directly on … the silicon" and two PCI Express controllers.
> SPARC systems offered, and still do offer, special hardware support
> for dynamic programming languages in which immediate integers have
> tag 00 in the bottom 2 bits.  However, when they went 64-bit, they
> didn't bother to extend that to 64-minus-2-bit integers.
>
> And of course there are Intel and AMD chips with all sorts of extra
> hardware support for all sorts of things.  Notably, people are
> integrating GPUs onto the same chip as the CPU.  (Where are the APL
> compilers that can take advantage of this?  It's the perfect
> APLlication for the language!)
>
> The key point is that cpu designers/vendors take existing workloads
> of commercial significance and figure out how to optimise that.  If
> a heavy-duty web server, or a high end gaming system, or a mobile
> phone, &c could clearly benefit from some kind of acceleration,
> someone will get it.  If Javascript had a common abstract instruction
> set, there'd be hardware acceleration for that.
>
> Haskell programs are not yet a workload of commercial significance.
>
> Sadly.
>
>



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