[Haskell-cafe] Specialized Computer Architecture - A Question

[Tommy Thorn]

And if you are, you may be interested in https://github.com/tommythorn/Reduceron

The underlying topic is a fascinating one. The fact that people ignore is that
silicon cycle time improvements have been fairly modest - perhaps 2-3 orders
of magnitude and we have long been at the point where wire delays are what
matters. Without significant innovation, silicon scaling would just have given you
a moderately faster cpu, but ridiculously tiny. Those innovations are countless,
pipelining, caches, superscalar, out-of-order, speculation, ...

Now that conventional single-threaded performance is peaking out, the time is
ripe to revisit functional machines and apply these innovations.

Reduceron is an amazing accomplishment (do and there are other projects in this
space too. I hope the research on this continues.

My only contribution here is to try to expand the usefulness of Reduceron
and get it running on cheaper hardware.  I would love more contributors,
especially on compiler side (using a "real" Haskell front-end would be just
lovely).

Anyway, check it out and play around. I'll be happy to help.


Tommy Thorn

On Mar 19, 2013, at 05:07 , Simon Farnsworth <simon at farnz.org.uk> wrote:

> OWP wrote:
> 
>> Ironically, you made an interesting point on how Moore's Law created
>> the on chip "real estate" that made specialized machines possible.  As
>> transistor sizing shrinks and die sizes increase, more and more real
>> estate should now be available for usage.  Oddly, what destroyed
>> specialized machines in the past seemed to be the same cause in
>> reviving it from the dead.
>> 
>> The ARM Jazelle interface - I'm not familiar with it's but it's got me
>> curious.  Has there been any though (even in the most lighthearted
>> discussions) on what a physical "Haskell Machine" could look like?
>> Mainly, what could be left to compile to the stock architecture and
>> what could be sent out to more specialized areas?
>> 
> You might be interested in looking at the Reduceron - 
> http://www.cs.york.ac.uk/fp/reduceron/ - it was an FPGA-based effort to 
> design a CPU explicitly for a Haskell-like language.
> 
> -- 
> Simon Farnsworth
> 
> 
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